Introduction: Cordic Algorithm Using VHDL

##This is the most clicked, popular contact in Google for VHDL implementation of CORDIC ALGORITHM to give sin and cos wave##

At present time, many a hardware efficient algorithms exist, but these are not well known due to the dominance of software systems terminated the many years. CORDIC is such an algorithmic program which is nothing merely a set of shift and impart logics exploited for computer science a wide range of functions including certain trigonometric, hyperbolic, analog and logarithmic functions. This is the algorithm victimised in calculators etc. Thus by just exploitation smooth shifters and adders we can design a hardware with less complexity but power of DSP using cordic algorithm. Hence IT can Be designed As bare RTL design in VHDL or Verilog without using whatever dedicated floating point units or complex math IPs.

Step 1: VHDL and Modelsim

Here the cordic algorithm is implemented using VHDL to generate a sine wave and cose wave . It can output sine and cosine of input angle at large precision. The cypher is synthesizable on FPGA. Modelsim is accustomed copy the design and the test work bench .

Step 2: VHDL Code for the Design and the Essa Judiciary

---- Guidelines ----

Binary scaling technique is used to represent floating point numbers.

Delight go thru the attached docs before you code.

Go thru
Simulating cordic_v4.vhd - The Design

-The input is angle in 32 bits + sign bit ; it can process any angle from 0 to +/-360 degree with input preciseness of 0.000000000233 degree. When giving input -> MSB is the sign routine and the rest 32 bits represent order of magnitude .

-The output of the aim is its sine and cos value in 16 bits + sign bit .ie; with precision 0.00001526. Please note that the output is displayed in 2's compliment form if the respective sin or cos lettuce economic value is negative.

Simulating testb.vhd - Test Bench For The Design

(1) Stimulus angles and pull reset ='0'. After two steps of computer simulation pull reset to '1' and " rivulet all ".

(2) In feigning windowpane set the radix of wickedness and cos signals as quantitative and format > Analog ( automatic ).

(3) Soar upwards out to see the waveform properly.

Step 3: Files Attached

(1) cordic_v4.vhd - Design .

(2) testb.vhd - Test workbench for the conception .

(3) Document along how to ram down angle inputs and convert the binary results.

Update: THESE FILES ARE OBSELETE AND NOT PROVIDED Any longer. PLEASE USE FILES FROM NEXT Stair.

Tread 4: Mini-Cordic Information processing Core - 16 Bit

Restriction of the above execution is

- slow, lower time frequency of operation because of doing computations in a single clock cycle.

Miniskirt-Cordic Informatics Core - 16 Scra

- Critical paths distributed to multiple cycles to improve performance.

- Faster - FPGA proven design synthesised upto 100 Mhz clock.

- More area optimised in HDL, Lesser ironware.

- Lode and Done Position signals added.

- Just downside is lesser declaration compared to the previous one.

Testbench:

completely automated from 0 to 360 degree angle inputs

Files Engaged:

1) mini cordic main vhdl file

2) mini cordic test bench

3) Mini Cordic Information processing Core manual of arms

4) Doc on how to force angles and convert results

For any queries, tone free to impinging Maine:


Mitu Raj

keep an eye on Pine Tree State: https://www.instructables.com/member/AmCoder/

mail: iammituraj@gmail.com


###Total downloads : 325 arsenic of till 01-05-2022###

### Code live on edited : July-07-2022 ###

Step 5: New Blog

I have launched my new website for my technical blogging. Sadly, I have to progress from instructables, where I have got the most support. Delight stay supporting Pine Tree State at Chipmunk System of logic. The web log is all about open-source codes and design techniques in VLSI digital design.

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